Ensuring trusted execution across multiple chiplets and vendors is more complex than in traditional monolithic SoCs.

Hardware Trojans Detection Using GNN in RTL Designs” was published by researchers at University of Connecticut and University ...

Disaggregration requires traffic cops and in-chip monitors to function as expected over time. The shift from SoCs to multi-die assemblies requires more and smarter controllers to be distributed ...

Analog and mixed signal content is adding risk to ASIC designs. Pessimists see the problem getting worse, while optimists point to AI and chiplets for relief.

New tools and techniques are being developed and can help keep the verification process secure, alongside a firm foundation of good design verification practices.

For many aspects of an EDA flow, hallucinations from AI are not really that serious, because that is no worse than engineers on a Friday afternoon.